Reserach On The Key Technology Of 340GHz Solid Transceiver

In recent years,technology of millimeter wave communication and radar systems have developed rapidly.Meanwhile,in order to meet the increasing demand of information interaction across various industries and individuals,researchers are seeking a transmission scheme which makes the data transmiting more rapidly and efficiently.In spite of the spectrum resources,terahertz radar also has the advantages of short wave length and high resolution,so it has been studied for many years.With the development of device technology,submillimeter and terahertz transceivers have achieved higher realizability,efficiency and reliability.The realizable high power frequency source is one of the key technologies in the RF and LO links in the transceiver system.Due to the lack of available amplifiers in the sub millimeter and terahertz band,the efficiency of frequency multipliers has a significant impact on the signal power.With the progress of planar Schottky diode technology,the hybrid integrated circuit using flip diodes becomes the commonly used method in the design of solid frequency multipliers.In this paper,technology of frequency multipliers of 340 GHz transceiver has been studied,and the design of170 GHz doublers,a 340 GHz doubler and Ka band triplers are given.The key devices of the 170 GHz and 340 GHz doublers based on the balanced structure are AS2/2G2/V4.1 and AS2/4G2/6p6 respectively.Each of the chips contends a series of reverse diodes.In this paper,the principle of balanced double frequency and the related circuit structure are analyzed,which mainly involves waveguide matching,waveguide microstrip coupling,and the matching circuit based on suspended microstrip line.The design and simulation of the above two frequency multipliers are carried out,and the corresponding processing schemes are given.Among them,the first version of the 170 GHz frequency multiplier has a simulated conversion loss of about 8d B in the band of 160-176 GHz.Measurements show the output power ranging from 7.6 to 42.6m W across the band of157?165GHz with the driving power of 177 m W.The conversion efficiency range from 4.8% to 24%and the peak efficiency is 24% at 159 GHz with the peak output power of 42.9m W.In the the second version,a conversion efficiency of more than 20% and a conversion loss of less than 7d B are simulated.Simulations show that the 340 GHz doubler achieves a conversion loss of 8d B in 334-343 GHz band and the peak conversion efficiency achieves 18.9% at 344 GHz.The key devices of the the Ka band tripler based on balanced structure are DMK2308 and AP-3J respectively.Each of the chips contends anti-parallel diodes.In this paper,the principle of balanced triple frequency multiplication and the related circuit structures are analyzed,mainly involving the design of the wide stop-band LPF,the wide pass-band BPF and the wide band matching circuit.The two versions of frequency multiplier with different chips are designed.The simulations show that both versions of the frequency multiplier can achieve a conversion loss of 19 d B.Among them,the version with AP-3J realizes a larger relative bandwidth and a higher conversion efficiency.