Research On High-speed Post-processing Technology In Continuous-variable Quantum Key Distribution Based On FPGA Implementation

In modern society,information security is directly related to various aspects such as national security,social stability,and personal privacy.Therefore,people are paying more and more attention.Quantum key distribution(QKD)offers information-theoretic security between two remote parties that employ one-time pad encryption to encrypt and decrypt messages using a symmetric secret key,even in the presence of an eavesdropper with infinite computing power and mathematical genius.A QKD system typically includes three steps:(1)quantum state preparation,distribution,and measurement;(2)data sifting and parameter estimation;and(3)post-processing procedure.The last procedure can be divided into two main parts,information reconciliation(IR)and privacy amplification(PA).IR uses error correction codes(ECCs)to correct errors in sifted keys to obtain identical corrected keys.PA eliminates the leaked information to an eavesdropper and distills a secret key by using universal hash functions.Continuous-variable QKD(CV-QKD)is an important category of QKD.It has simple detection equipment,good compatibility with existing standard optical communication components,and potential higher secret key rates over metropolitan areas.However,the post-processing procedure in CV-QKD systems is relatively sophisticated,which becomes one of the key bottlenecks restricting system performance.In a CV-QKD system,the computation speed of the post-processing procedure inevitably affects the practical secret key rate.IR and PA can be implemented in parallel using low-density parity-check(LDPC)codes and hash functions,respectively.Therefore,they can all use parallel process methods to improve the computation speed.As a mature large-scale programmable device,Field programmable gate array(FPGAs)have very good parallel processing capabilities,and can be customized by users according to the needs of programming.The main research purpose of this paper is to use FGPA hardware acceleration technology to improve the computation speed of post-processing in CV-QKD systems and promote its practicality.The main work includes:1.FPGA design and implementation of the high-speed slice reconciliation scheme.When implementing the slice reconciliation,the layered sum-product algorithm decoders and a modified LDPC codes construction algorithm adapted to FPGA's characteristics are developed and employed.Two different architectures including multiplexing and non-multiplexing are designed to achieve the trade-off between the speed and area of FPGAs,so that an optimal scheme can be adapted according to the requirement of a practical system.Simulation results show that the maximum throughput can reach 100.90 M symbols/s.We provided some possible solutions to obtain better performance when more advanced FPGAs are available.2.Implementation of high-efficient multidimensional reconciliation scheme.We briefly introduce the principles of multi-edge type LDPC codes and multidimensional reconciliation scheme.Based on the previous work,a multi-edge type LDPC codes with good decoding performance is constructed to achieve high-efficient multidimensional reconciliation.The maximum reconciliation efficiency can reach 99.01%.3.FPGA design and implementation of high-speed PA algorithm.The computation speed of using the CPU to perform the PA algorithm cannot meet the requirements of systems,and the finite-size effect further increases the amount of data,which puts higher requirements on the processing speed.Based on the characteristics of FPGA,this paper proposes a rhomboid-block operation,which transforms element processing into block processing in the PA algorithm,which greatly shortens the calculation time.The algorithm also effectively reduces the required on-chip BRAM storage resources of FPGAs,and can size-adaptive to a different input and output lengths.This solution can be applied not only to the CV-QKD system but also to other QKD systems and even classic communication.4.Overall FPGA implementation of post-processing procedure.Combining slice reconciliation and PA to realize the overall post-processing process,so as to realize the real-time key extraction of CV-QKD systems.When the signal-to-noise ratio is 3.0,the computation speed can reach 38.18 M symbols/s.The scheme can effectively reduce the power consumption of the CV-QKD system and promote the miniaturization and integration of the system.