Design And Implimentation Of Multi-level Cache Architecture For High-performence Router

With the development of network,people's demand for the network is rich,routers need to complete more complex processing of data packets,so as to provide users with more functions and better quality of service(QoS).The single port rate of high-performance router is getting faster and faster.In order to deal with the massive data packets buffered during link congestion,it is difficult to realize the process design of router by increasing the storage space of router infinitely,and the end-to-end processing delay due to more complex processing process cannot be improved.If you want to further improve the performance of the router,you can start from the router storage system,increase the bandwidth of the router storage system,so that you can process more network packets per unit time.Therefore,this project has carried out the research on the storage architecture of high-performance router,and designed a multi-level cache architecture based on hybrid SRAM/DRAM storage system.To learn the multi-level cache architecture,we need to reserve enough storage space for the on-chip cache to cache the packets to be forwarded,and design a refined storage management scheme for this purpose.It includes analyzing the requirements of multi-level cache architecture for on-chip cache,partitioning the on-chip cache and defining the minimum memory unit of different partitions;In order to make more effective use of the packet storage area in the cache on chip,a partner cache space management algorithm is designed to reduce memory fragmentation and accelerate memory allocation;Considering the problem of multi-core using shared memory,a parallel storage scheduling scheme based on peer cache space algorithm is designed.Secondly,the router multi-level cache architecture is designed on he premise that the cache on chip supports packet storage and forwarding.Its functional modules include cache space management module,which is used for cache switching control and allocating appropriate cache space for router storage requirements;The flow classification module is responsible for flow classification and access control,and the results of flow classification serve the whole multi-level cache architecture;The queue scheduling module and the collaborative cache space management module complete the scheduling and forwarding of each stream queue in the multi-level cache architecture.Finally,the capacity of on-chip cache space is estimated to judge the rationality of the storage management scheme.Simulation and performance optimization of the partner cache space management algorithm and Its Parallelization scheme are carried out.Based on ns-3,the multi-level cache architecture simulation is built,and on this basis,the cache switching control algorithm and queue priority scheduling algorithm are further simulated to verify the improvement and optimization of the architecture performance.