Convolutional Neural Network Research And FPGA Implementation For Handwritten Digit Recognition

Convolutional Neural Networks(CNN)are widely used in image classification,speech recognition and target detection due to their good non-linear fit.With the development of CNN,the size of the model and the amount of calculations have increased dramatically,leading to the fact that CNN can only be used on specific platforms and cannot be specialized and miniaturized.Field Programmable Gate Array(FPGA)has the characteristics of high performance,low power consumption,reconfigurability.When designing CNN acceleration,it can make full use of its internal concurrency and parallelism to improve the efficiency of convolution operation.Therefore,in order to improve the computational efficiency of CNN model and reduce the resource and power consumption of the model.This paper studies the accelerated design of the model reasoning process and the application of handwritten digital recognition based on FPGA development platform.By learning the principle,structure and data processing process of CNN,this paper uses model optimization and hardware acceleration to accelerate the CNN model.In terms of model optimization,a handwritten digit recognition model RLeNet,which is more suitable for hardware platform implementation,is realized by optimizing the structure and parameter of LeNet-5 model.In terms of hardware acceleration,this paper implements the CNN hardware simulator by C language,analyzes the maximum parallelism of each layer of CNN,and explores the possibility of model optimization acceleration from two aspects of hardware implementation and resource occupancy.After that,this paper realizes the design of RLeNet accelerator by hardware and software collaboration on FPGA platform.The software part realizes the collection,processing and transmission of the handwritten digital pictures to be tested,and the hardware part realizes the hardware acceleration and optimization design of RLeNet.In the hardware acceleration part,this article adopts a bottom-up approach.First,it realizes the design of convolution,pooling and communication modules.Then,it optimizes and accelerates through parallel structure optimization,word length selection,resource reuse and parallel pipeline.Finally,it completes the design of RLeNet overall data path.After the design of the handwritten digit recognition RLeNet accelerator is completed,it will be packaged into a general handwritten digit recognition accelerator IP and tested.The test results show that the accuracy of accelerator IP is 96.18%.At 200 MHz clock,the model predicts that the time of a picture is about 20.3?s,power consumption is 0.419 W,and the resource consumption accounts for about 1 / 3 of the system resources.In addition,this paper set up a measurement platform for handwritten digit recognition.The images are captured by the upper computer camera and sent to the lower computer accelerator.The accelerator receives the images and predicts them,then outputs the prediction results.