Convolutional Neural Network Algorithm And FPGA Implementation For Handwritten Digit Recognition

Handwritten digit recognition is essentially an image recognition problem.In recent years,in the field of large-scale application of image digital recognition,Convolutional Neural Network(CNN)has been widely used relying on outstanding performance in algorithm performance.However,CNN,as a computationally intensive and storage-intensive multi-layer neural network,faces the challenge of efficient hardware implementation.Field Programmable Gate Array(FPGA)is one of the most attractive implementation platforms for hardware acceleration of computationally intensive algorithms due to its high performance,low power consumption and programmable features.Therefore,how to implement high-performance convolutional neural network system for handwritten digit recognition on FPGA has important theoretical research significance and practical value for the development of image recognition.Firstly,this thesis studies the hardware-friendly CNN operation model,and determines the specific algorithm of CNN when considering the circuit complexity and algorithm recognition rate,and completes CNN training,testing and parameter extraction on MATLAB.At the same time,in order to implement CNN with high performance on FPGA,this thesis studies the parallel characteristics of CNN calculation,various hardware implementations of activation function and algorithm strength reduction characteristics of fast algorithm.Then,this thesis proposes two hardware acceleration schemes for CNN implementation.Scheme 1 is a CNN accelerator design based on a cyclic transformation method that flattens all layers of a convolutional neural network on a hardware architecture such that it is suitable for CNNs with a small number of layers.Among them,the cyclic transformation method calculated by CNN can realize efficient parallel pipeline circuit to improve throughput(Throughout,unit: GOPS: Giga Operations Per Second).Scheme 2 is a CNN accelerator design based on fast filtering algorithm.This scheme designs a hardware architecture of layer-by-layer acceleration of convolutional neural network,which makes it more scalable and suitable for CNN with deeper topology.Among them,in order to reduce the calculation amount of CNN,a two-dimensional fast filtering algorithm is introduced into CNN to improve throughput and reduce hardware resource consumption.Finally,the system test platform was built on the Xilinx kintex-7 KC705 development board,and the designed CNN accelerator was tested and analyzed using the handwritten digital set MNIST.For scheme 1,when the input clock is 150 MHz,the throughput of the circuit is 20.62 GOPS,the recognition rate of digital characters is 98.68%,and the hardware resources of DSP(Digital Signal Processing)occupy 565.For Option 2,when the input clock is 100 MHz,the throughput of the circuit is 20.49 GOPS,the recognition rate of digital characters is 98.48%,and the DSP hardware resources occupy 284.Compared with the related literature,the CNN accelerator implemented in this thesis can effectively improve the throughput rate.