Research On Silicon-based Novel Gate-all-around Nanowire Device

Ultra-low power and high-performance logical devices has been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable.While system scaling enabled by the Moore's law is facing challenges due to the scarcity of resources such as power and interconnect bandwidth.Constrained by the limited capacity of battery,portable electronic devices are hard to have "always-on" feature and have to be recharged frequently,causing great inconvenience to users.To reduce the overall power consumption,researchers have worked out a number of ways to reduce the off-state current of CMOS devices.By fabricating the whole system on a SOI wafer,the stand-by current of the system can be greatly reduced due to the low off-state current of SOI MOSFET.But the SOI MOSFET has self-heating effect which increases device operating temperature,reduces carrier mobility as well as causes performance degradation.By introducing new physical mechanics into CMOS devices,researchers are able to lower the subthreshold slope of transistors hence reduce the leaking current of whole system.This type of devices includes Impact Ionization MOS(IMOS)and Tunnel Field Effect Transistors(TFET).Technically,IMOS is a reverse biased p-i-n diode with a control gate.The control gate is used to control impact ionization phenomenon between two junctions.The avalanche breakdown is very fast and gated diode pulsed into breakdown can show subthreshold slopes much lower than 60mV/decade,thus exhibits lower off-state current compared with a conventional MOSFET.However,due to the need of drastic doping profile,the fabrication of IMOS requires costly millisecond annealing techniques which greatly limits its application.Tunnel field effect transistor is designed using band-to-band tunneling effect.The carriers are injected by band-to-band tunneling effect from valence band of source for a N-type TFET,which is totally different from conventional CMOS devices that use thermionic emission.The physical mechanics of TFET allows them not to be constrained by the Boltzmann limit(about 60mV/decade at room temperature).Thus,TFET has the potential to be used as low-power devices for its extremely low off-state current.However,the TFETs fabricated are not competitive with conventional MOSFETs which are based on thermionic emission.Low on-state current and high average subthreshold slope are main limitations of TFET devices.Gate-All-Around(GAA)CMOS FET is based on conventional CMOS FET,it features a circular gate around the channel.GAA MOSFET is compatible with existing CMOS fabrication process,it has the superior electrostatic control compared with FinFET and planar CMOS FET.The ITRS predicted that beyond 2020,a transition to Gate-All-Around and vertical nanowires devices will be needed when there will be no room left for the scaling because GAA devices are the ultimate structure in terms of electrostatic control to scale to the shortest possible effective channel length.While we found the potential of GAA devices are not fully discovered,and it's necessary to explore any new GAA structure to help reduce system power dissipation.Based on conventional Gate-All-Around nanowire transistor,this thesis proposed two novel Gate-All-Around nanowire structures,Core-Insulator Gate-All-Around nanowire transistor and Core-Substrate Gate-All-Around nanowire transistor,respectively.Core-Insulator Gate-All-Around nano wire transistor features a Core-Insulator inside the channel,it can cut off the leaking current path,therefore reduce the static power dissipation.Core-Substrate Gate-All-Around nanowire transistor features a Core-Substrate,which works with gate to enhance channel controllability,therefore it can help to boost the performance.Two structures are different and novel,by changing the material of Core-Insulator,Core-Insulator Gate-All-Around nanowire transistor can have lower gate capacitance than that of conventional Gate-All-Around transistor,so as to run at faster speed.Core-Substrate Gate-All-Around nanowire transistor has lower static power dissipation than that of conventional Gate-All-Around transistor,besides,the introduction can make device performance less dependent on device dimension.Furthermore,the radio frequency performance of Core-Substrate Gate-All-Around nanowire transistor is superior to that of conventional Gate-All-Around transistor,but it has a relatively larger gate capacitance.Based on existing silicon-based fabrication process,this thesis proposed fabrication process of Core-Insulator Gate-All-Around nanowire transistor and Core-Substrate Gate-All-Around nanowire transistor.The Simulation results show that both of the two structures are better than conventional Gate-All-Around transistor,they are suitable candidate of future generation low power and high-performance integrated circuit.