Simulation?preparation And Characterization Of Silicon Carbide MOS

As the third-generation semiconductor material,silicon carbide(SiC)has the advantages of wide band gap,high saturation drift speed,high pressure and high temperature resistance and radiation resistance.Therefore,the power device based on SiC can achieve smaller conduction state,faster switching speed,higher working temperature and radiation resistance,and has more extensive and excellent application.However,due to the high density of state at SiO₂/SiC interface,SiC power devices have low inversion layer mobility and poor gate oxygen reliability.At present,post oxidation annealing in nitrogen environment is the best way to improve the interface quality and improve the mobility to a certain extent,but it is far from the theoretical value,which often leads to gate oxide reliability problems.And it is not clear how annealing can improve the micro defects of devices,and the research on the micro mechanism of defects is insufficient.Therefore,it is necessary to study the influence of the micro defects of SiO₂/SiC interface on the electrical properties of devices.In this paper,the electrical properties of two n-type SiC MOS samples were measured and characterized by High-Low method and low temperature conductivity method.Using sentaurus TCAD software,the capacitance model of SiC MOS including SiO₂/SiC interface trap and near interface trap in oxide layer is established and C-V characteristics are simulated.The simulation results of SiC MOS based on tunneling model and defect model show that,the interface trap charge mainly affects the accumulation and depletion regions of the C-V curve.The shallow level interface traps mainly affect the capacitance of MOS and reduce the threshold voltage of C-V curve,and the deep level interface trap makes the C-V curve drift.High density interface traps will not only affect the size of MOS capacitor,but also cause serious C-V curve drift.The C-V curve appears hysteresis due to the trapped charge near the interface.As the energy level of the near interface trapped charge is further away from the bottom of the SiO2conduction band,the hysteresis voltage first increases and then decreases.The influence of the low concentration near interface trap is small,and the high concentration near interface trap charge makes the hysteresis voltage of C-V curve increase rapidly.The fixed charge of the oxide layer makes the C-V curve drift in the direction of adding negative gate voltage,and the higher the fixed charge concentration is,the greater the C-V curve drift value is,which affects the performance of the device.The C-V characteristic curve of the samples at the same temperature shows that the positive deviation of the flat band voltage?V_FBand the flat band voltage difference?V_fbof the NO post-oxidation annealing sample is significantly smaller than that of the NO post-oxidation annealing sample,and the interface state density D_italso decreases significantly.This shows that the NO post-oxidation annealing has an obvious effect on improving the interface state density.The C-V characteristic curves at different temperatures show that the?V_FBvalue and?V_fbvalue of the NO post-oxidation annealing sample at room temperature are almost the same as those of the sample without annealing,but the D_itis significantly different.The?V_FBvalue and?V_fbvalue of the two samples at low temperature are quite different,and the difference in D_itis smaller than that at normal temperature.The results of the interface state density extracted by the conductance method show that the NO post-oxidation annealing treatment can reduce the interface trap density at the deep level,but it can't suppress the change of the interface trap density at the shallow level,the shallow level interface trap is greatly affected by temperature.The low-temperature conductivity method is used to effectively extract the interface state density at the energy level below 0.1e V from the conduction band.The interface state density detected in a wide energy level range(0.02e V-0.5e V)includes the extraction at the shallow level interface traps and near-interface traps extracted at deeper levels,and these two types of traps can only be distinguished at lower temperatures(<100K),which is mainly due to the conductance signal caused by the electron tunneling effect at low temperatures Stronger.The time constant of the near-interface trap and the law of the corresponding energy level of the capture cross section do not conform to the theoretical law of the general trap reported previously,and have different effects on the device performance.Two different electron tunneling mechanisms are proposed:when the applied gate voltage biases the MOS to depletion,electrons undergo"reversible"tunneling between the conduction band of 4H-SiC and the near-interface trap,which is independent of temperature.When the MOS is biased towards the flat band or accumulation,the electrons in the conduction band of 4H-SiC can be trapped by near-interface traps with the same energy level,and"irreversible"tunneling occurs.This process is highly related to temperature.Based on this mechanism,the reason why the near-interface trap can only be extracted in the range of lower temperature and middle and low energy levels is explained.At the same time,a rational analysis is made on the study of the near-interface trap using hysteresis.