Study On The Dynamic Avalanche Degradation And Failure Mechanism Of SiC Based 1200V VDMOSFET

Silicon carbide（SiC）power VDMOSFET（Vertical-Diffused MOSFET）which is widely used in various power conversion systems processes the advantages of high block voltage,high frequency applications,low power consumption and low on-resistance that demonstrates the potential to replace the traditional silicon（Si）power MOSFET and IGBT（Insulated Gate Bipolar Transistor）.However,compared with mature Si devices,SiC power VDMOS is far from its material limitation.The problem of dynamic degradation has become the main reason for limiting the function and lifetime of devices.Therefore,an in-depth study of the dynamic failure of SiC power VDMOS is urgently needed in order to improve the reliability of the device.SiC power VDMOSFET is often used in high-frequency power circuits for its perfect dynamic characteristics.The dynamic avalanche failure originated from the energy released by parasitic elements or accidentally trigger during dynamic operation has become the limitation of the device performance.Therefore,simulation and experimental research on the single pulse UIS（Unclamped Inductive Switching）avalanche failure of SiC power VDMOSFET is conducted in this paper.At present,the three mechanisms of parasitic BJT opening,aluminum electrode melting and channel activation were considered to be the possible causes of UIS failure.However,the main UIS failure of SiC power VDMOSFET is undetermined due to the lack of feasible junction temperature observation methods and accurate simulation models.First of all,the turned on possibility of parasitic BJT caused by the body series resistance R_B under the high electrothermal stress of UIS is theoretically discussed.Then,an electrothermal simulation model of SiC power VDMOSFET which could be used to analyze the transient UIS process is established in TCAD software.In this model,the high temperature,high voltage and large current characteristics in the UIS process were fully considered in setting appropriate thermal conduction structure,thermal parameters and thermal boundary conditions.More importantly,the avalanche ionization model is revised based on the latest experimental data,so that the simulation can reflect the effect of temperature on the breakdown voltage accurately.This model is proved to be accurate by comparing the output curves of simulation and experiment in different I_DSmax.The half-cell simulation which is based on the actual device parameters shows that the threshold turn-on current of parasitic BJT is 54A,while a 4%decrease in the P-well doping concentration would cause this threshold current decreased to 43.3A which is the average avalanche current of failed devices.This implies a possibility of parasitic BJT turn-on in real applications.Simulation result could not explain the burning of SiC epitaxial layer and the formation of hot observed in experiment although the maximum junction temperature at I_Dmax=43.3A has reached about 950K which exceeds the melting point of aluminum（933K）.So it is believed that the aluminum electrode is not the cause of device failure.In addition,the test results also show that the gate characteristics are not degraded before UIS failure,so the channel activation is not believed to be the cause of device failure either.The 4-cell simulation shows that the hot spots observed in the experiment could only be explained by the turn-on of parasitic BJT for the concentration of current and temperature inside the device.Therefore,this paper believes the parasitic BJT turn-on is the main cause of the device failure under single pulse UIS stress,and the avalanche robustness could be enhanced by suppressing it.Further research shows that the body series resistance R_B could be effectively reduced through good P-well doping,P+doping,and P+ohmic contact.The device junction temperature could be effectively reduced by selecting appropriate electrode metal and surface thermal conductive glue.And the turn-on of parasitic BJT in advance could be effectively avoided by improving the process level.In the future,in design and manufacturing,parasitic BJT turn-on can be suppressed by reducing the body series resistance R_B,lowering the junction temperature,and improving process to improve the device avalanche robustness.