FPGA Implementation Of Signal Processing Algorithm For Millimeter Wave Ground Battlefield Reconnaissance Radar

Ground battlefield reconnaissance radar is mainly equipped in the army.It is used to alert and detect the enemy's moving personnel,vehicles,tanks and other targets,determine their positions,distances and moving routes,and provide information about the enemy's ground activities.With the continuous improvement of the performance of radar equipment,the radar has higher requirements for the computing power and real-time performance of signal processing systems.As a digital signal processing chip,FPGA has the characteristics of parallel computing and processing of large bandwidth data.It can meet the computing power and real-time requirements of radar signal processing,so it is widely used in radar signal processing.This thesis takes the millimeter-wave ground battlefield reconnaissance radar project as the background,first introduces the working principle of the linear frequency modulation continuous wave radar,analyzes the echo forms of different transmission waveforms,and method of solving target distance and velocity from difference frequency signal.In order to solve the two problems of velocity ambiguity and multi-target pairing,this paper introduces the method of velocity defuzzification and target pairing based on frequency domain.Based on the digital signal processing hardware platform and system requirements,an FPGA-based signal processing system architecture for ground battlefield reconnaissance radar algorithm is designed,and the working principle of each module in the architecture and FPGA implementation method are introduced.In view of the low reading efficiency,the imbalance of reading and writing efficiency and the interruption of reading and writing operations in the conventional matrix transposition scheme,this paper proposes a matrix transposition scheme which combines row segmentation with multi bank ping-pong reading and writing.The row segmentation method reorganizes the row of matrix into a small matrix before the matrix is written into DDR3.It not only increases the number of row switching of matrix write operation,but also reduces the number of row switching of matrix read operation,improves the read efficiency and solves the problem of unbalanced read-write efficiency.In the multi bank ping-pong read-write scheme,the read or write operation monopolizes one bank and exchanges banks after each transpose.This solution solves the problem of mutual interruption of reading and writing process in matrix transpose operation.In the system,the barrel buffer structure and pipeline CFAR module are combined to avoid the second matrix transposition between MTD and CFAR processing,and reduce the processing delay and resource consumption of the system.The FPGA signal processing architecture described in this paper is based on xc7z100 series chips of Xilinx company.Each processing link in the signal processing architecture adopts the modular design method.The signal processing architecture is verified by function,integrated implementation and timing analysis.After the design and implementation,the main logic resources consumption is less than 25% of the total resources,all nodes meet the timing constraints,and the system can complete signal processing tasks efficiently and stably.