The Module Level Verification Of SMC2.0 Based On UVM

With the rapid development of intelligent technology and the deepening of social intelligent informatization,data as a carrier of information has evolved into a core asset.However,along with the leakage of personal privacy,the security problems such as the cracking of data content are emerging day by day,and the security of computer data is getting more and more attention.DDR is a very common volatile memory.Many modules in the chip system,such as CPU,DMA and CE,will access DDR,mainly for data storage and reading.Therefore,DDR storage system plays a key role in data security protection,and it is often the preferred target of malicious attackers.At present,there are many researches on the data storage security protection technology for non-volatile memory,but there are few researches on the data storage security protection technology for volatile memory,so the data security of DDR storage system has become an important research direction in the field of security.SMC2.0 is the security control module on the upper layer of DDR to ensure the security of access to DDR by other host modules in the So C system.It has a relatively complex internal structure and functions,such as regional division of DDR,security authentication of many master commands,addition and resolution of data,encryption and decryption,etc.Therefore,it is of great research value to select the authentication method of this kind of volatile security storage controller,the design of the authentication platform and the optimization scheme of the authentication platform.In order to design a more complete validation platform,improve the automation capability of validation,and improve the reusability of the validation platform and its interaction with other languages,so as to improve the validation efficiency.Starting from the study of various functions and communication protocols of SMC2.0,this paper adopts UVM verification methodology and realizes the functional verification of SMC2.0 modules through System Verilog language.It mainly realizes the design of the overall architecture and components of the validation platform,and focuses on the development of the reference model for the validation of the HIF protocol for VIP and the simulation of various functions of SMC2.0.Achieve functional coverage by designing functional coverage files and test cases.Complete the design quality assessment of the SMC2.0 module by analyzing the code coverage.Also focuses on the role of the script in the verification efficiency,in the realization of verification platform and the use case,on the basis of study of the way using Perl script tool processing Excel generated DUT and related macro definition file verification environment,when different projects need different versions of SMC2.0 convenient access to its validation environment,to achieve automation of reuse.The main research contents and results of this paper are as follows:Firstly,Based on the research on the function and communication protocol of SMC2.0,the verification points are extracted.The verification scenario was constructed by cross-covering each function point,so as to realize data transmission in the most complex verification scenario using the normal transmission mode of HIF protocol and the outstanding transmission mode respectively.Secondly,study UVM validation methodology,and use UVM basic class library to build a validation platform.Design validation components such as agent,driver,monitor,etc.,focus on designing reference models based on various validation scenarios,and design VIP general validation model based on HIF communication protocol.In order to solve the different project SMC2.0 demand for verification platform different questions,this topic selection,by means of artificial configuration Excel on the basis of the basic authentication environment through the design process the Excel Perl script to realize flexible adaptation of different project SMC2.0 verification platform,greatly shorten the verification platform design time,improve the verification efficiency.Thirdly,design the underlying sequence and the top-level virtual sequence based on the extracted verification points,and build different test scenarios to cover all the functional points of SMC2.0.Fourthly,design the function coverage file,implement efficient regression verification through the design of Perl regression script,and complete the function coverage collection for SMC2.0.Through the DVE software analysis coverage collection situation,through the directional test to achieve code coverage and functional coverage standards.The waveform of each typical test case was analyzed by Verdi software.