Simulation Design And Optimization Of 4H-SiC VDMOSFETs

As a kind of wide bandgap semiconductor,4H silicon carbide(4H-SiC)has superior physical and electrical properties,such as high thermal conductivity,high electron saturation velocity,high critical electric field,which make it the most promising material for the applications of high temperature,high frequency,and high power semiconductor devices.Currently,vertical double-implanted MOSFET(VDMOSFET)is one of major structures in power MOSFETs,and 4H-SiC VDMOSFETs are considered as an ideal choice to replace Si bipolar power devices owing to their low ON-resistance and absent minority carrier storage.However,due to the existence of the JFET region,4H-SiC VDMOSFETs exhibits a large ON-resistance.This work focuses on the research and design of 4H-SiC VDMOSFETs.By optimizing the JFET area,the on-resistance of the device is reduced,and the FoM is improved.The specific research content and results are as follows:(1)In this work,we propose a new method to calculate the best design parameter of the drift layer via computer-aided way.The breakdown voltage of the device and the resistance of the drift layer are abstracted as a function of the thickness of the drift layer and the doping concentration.Under the premise of satisfying the desired breakdown voltage,the combination of the minimum thickness and the doping concentration of the drift layer resistance is found by numerical calculation.For 4H-SiC VDMOSFETs with a blocking voltage of 1700 V,the best design for the drift layer got by this method is with a thickness of 11 ?m and a concentration of 9×1015 cm-3.We studied the effects in detail of design parameters like P-Well concentration and thickness,JFET concentration and width,oxide layer thickness,the fixed charge on SiC/SiO2 interface,on device performance via Silvaco ATLAS.By the FoM parameter of the designed cells,we confirm the best design for the no-doped-JFET cell and const-doped-JFET cell.(2)Next,we do some work for optimization.In the optimized structure,two high ndoped regions are added at both sides of the JFET region.The additional high n-doped region could limit the expansion of the depletion in the JFET region at ON-state and inject electrons into the lightly doping JFET region,which is beneficial for the low Ron,sP.When the VDMOSFET is in the forward blocking mode of operation,as the drain voltage is much higher than that in ON-state,the expansion of the depletion region could still extend to the whole JFET region and well protects the gate oxide layer.The electronic properties of no-doped-JFET,const-doped-JFET,and optimized structure are compared in detail.The effect on the device performance caused by the high n-doped region width and doping concentration are also discussed.Simulation results reveal that the additional n-doped regions not only effectively limit the depletion width in JFET region at ON-state,but also could protect the oxide layer at OFF-state due to depletion expansion.As a result,the optimized structure reduces the specific ON-resistance by 18%while keeping breakdown voltage as roughly high as the conventional structure;meanwhile,the value of figure of merit increases by 22%,which exhibits a significant improvement in device performance.