Research And Implementation Of 3D IC's Floorplanning Method

With the rapid development of integrated circuit industry,research about 3D IC technology based on TSV has become hot.In 3D IC design flow,floorplan is quite important and a reasonable floorplan can bring many benefits.A good floorplan can help to achieve smaller area,higher integration and better performance on the chip.In this thesis,we will study 3D IC floorplan method and apply this method to the circuit design.Firstly,3D IC related problems are discussed,including TSV technology and 3D IC design flow based on TSV.In this part,we focus on TSV structure,RLGC model and TSV physical library definition.Secondly,on the basis of existing 3D IC floorplan method and simulated annealing algorithm,we propose a multi-objective optimized 3D IC floorplan algorithm considering chip area,wire length,temperature,number of TSV and chip integration and call the algorithm FP3 D for short.Then,we use MCNC benchmark circuits to verify the proposed algorithm.Compared with the existing 3D IC floorplan method,the experimental results show that FP3 D algorithm can help designers to achieve more reasonable floorplan results.According to the results,FP3 D algorithm improve chip area,wire length and average temperature a little,as well as decrease peak temperature by about 5%.At the same time,chip integration is improved above 15% and TSV number is decreased by 8%.Finally,FP3 D algorithm is applied to real circuit design.With SMIC 65 nm process,2D IC design is partitioned by hierarchy design flow.And FP3 D algorithm is used to achieve a 3D IC floorplan result.