Design Of Low Noise And Fast Response LDO

Microelectronic systems are running faster and faster,and the requirements for the power supply system are becoming more and more stringent.As an important part of the power supply system,the Low Dropout Regulator（LDO）is also facing increasingly stringent requirements,including faster response speed,lower noise,higher power rejection ratio,lower power consumption and higher integration,but there is no solution that can meet all the requirements.Aiming at the power supply requirements of high-speed and high-precision systems,this thesis uses a standard 28nm CMOS process and 1.9V power supply voltage to design an LDO with low noise and fast response performance without off-chip capacitors.The maximum load current is 50m A.First of all,for the low noise requirement,the LDO is connected in the form of unity gain to avoid amplifying the equivalent input noise of the error amplifier and the noise of the reference voltage.A level shift circuit is connected after the bandgap reference source to shift the bandgap reference voltage,and a low-pass filter is connected between the level shift circuit and the error amplifier to isolate the noise of the reference source,which makes the error Amplifier noise dominates the LDO output noise.The MOS tube bias current source that produces larger noise in the error amplifier is replaced with a triode bias current source,and the area and transconductance of the input pair of tubes are increased to reduce the equivalent reference noise at the input end.In this paper,in the frequency band of 10-100k Hz,the output integrated noise of the LDO is 7.3(1.Secondly,the requirement for quick response is achieved through two aspects.One is to increase the bandwidth of the error amplifier,add a source follower structure between the differential op amp and the power tube,and further reduce the output impedance of the source follower through the triode,so that the gate pole of the power tube is located at a higher frequency,and enhances the To drive the gate of the power tube,N-type MOS tube is used as the power tube,and the source stage is used as the output end,which reduces the impedance of the output end and makes the output pole of the LDO also at high frequency.These two methods can greatly improve the bandwidth.,to optimize the transient response of the LDO.The second is to increase the slew rate enhancement circuit（SRE）,which can increase the charge and discharge current of the power tube grid by detecting the transient change of the LDO output voltage,greatly improve the voltage slew rate of the power tube grid,and effectively reduce the output voltage.Undershoot and overshoot values.According to the simulation results,the load current jumps 50m A within 10ns,the output undershoot voltage does not exceed 70m V,the recovery time is less than 40ns,the overshoot voltage does not exceed 60m V,and the recovery time is less than 30ns.Finally,in order to improve the reliability of the chip,an over temperature and over current protection function is added.The over-temperature protection has a hysteresis function to avoid the repeated startup of the chip caused by temperature fluctuations.The over-current protection also has a hysteresis effect,which avoids repeated switching of the power tube due to load fluctuations.At the same time,the over-current protection is designed as a foldback protection structure to avoid output There is still a large current through the short circuit.