Digital Logic Design Of 10GSPS PXIe Oscilloscope Module

The acquisition of sporadic,aperiodic,and wideband signals is of great significance in fields such as electronic countermeasures,and radar communications.This usually requires the acquisition system to have higher analog bandwidth,sampling rate,storage depth,data throughput per unit time and other performance indicators.Therefore,it is very important to design data acquisition modules with high sampling rate.In this thesis,we designed a 10 GSPS time-interleaved ADC sampling（TIADC）oscilloscope acquisition system based on the PXIe bus,and the high-speed data receiving and synchronization technology,high-speed data transmission,large capacity storage and digital trigger technology are studied.The main tasks of this project are as follows:（1）Design of the overall hardware scheme of the acquisition module.First,we design a clock scheme that meets the requirements of the system according to the actual clock requirements of the system.Second,according to the function of each digital module of the system,the specific implementation scheme of synchronous data receiving,triggering,large capacity storage and PXIe interface communication is designed.Finally,the overall system hardware implementation scheme is presented.（2）Design of synchronous receiving and processing module for high-speed data.The principle of JESD204 interface and the working mechanism of JESD204 B deterministic delay are analyzed.The deterministic delay function supported by JESD204 B subclass-oneis used to realize multi-channel data synchronization.According to the high-speed data link transmission requirements of data sending and receiving,the corresponding high-speed data receiving and processing circuit is designed.The register communication between hardware and upper computer is designed based on AXI4 protocol.（3）Design of Trigger with deep storage module.On the basis of completing the design of ordinary digital trigger and digital window trigger function,we study the MIG control logic based on AXI interface,and we have realized the correct read and write control of external memory.Using FIFO as a buffer and trigger signal to divide the entire storage space,the design of segmented storage function is completed,and the collection of continuous occasional signals is realized.The experimental results show that the designed acquisition module can meet the expected requirements.