Research And Implementation Of Precise Delay And Narrow Pulse Trigger Technology For Sampling Oscilloscope

Signal test and analysis instrument is an important equipment in electronic communication,aerospace and national defense science and technology.The sampling oscilloscope based on sequential equivalent sampling technology can realize the equivalent acquisition of high-frequency periodic repetitive signals such as microwave and radar with low real-time sampling rate for analysis.The development of sampling oscilloscope is of great significance to the fields of communication,electronics and national defense in our country.The sampling oscilloscope needs a synchronous clock or frequency division clock of the measured signal to trigger during sampling,In order to realize the equivalent time sampling of high-speed digital communication signals,this thesis studies and designs a high-speed clock recovery circuit,which is used to obtain the clock signal synchronized with the measured signal from the high-speed data stream and this clock signal is used to trigger the sampling oscilloscope.On the other hand,in order to achieve high bandwidth transient equivalent time sampling,the trigger signal needs further compression and sequence delay,Therefore a pulse compression circuit and cascade delay circuit based on step recovery diode are designed and developed.Combined with the project,the research contents of this thesis are as follows:（1）In order to obtain the synchronization clock of the measured high-speed communication signal,this thesis first studies and designs the high-speed clock recovery circuit,and realizes the clock recovery of serial input data from 6.5 Mbps to6.25 Gbps in full rate clock mode and half rate clock mode.The experimental test shows that the recovered clock can be used to trigger sampling in sampling oscilloscope.（2）Based on the principle of sequential equivalent sampling,this thesis designs a cascade delay circuit which combines coarse delay and fine delay,a cascade delay circuit combining coarse delay and fine delay is designed in this thesis.Coarse delay part by coarse delay synchronization clock count,which can realize the delay time of microsecond level.The fine delay is realized by the delay chip.The delay range is 0 ～10.2ns,the delay resolution can reach 10 ps.（3）In order to realize the trigger sampling of the sampler,based on the study of the trigger signal of ultra narrow pulse.An ultra wide band（UWB）narrow pulse generation circuit based on step recovery diode（SRD）is designed,the narrow pulse trigger circuit compresses the sampling pulse to achieve picosecond voltage jump.The measured value is 95 ps,and the jump amplitude can reach more than 7V.The equivalent time sampling of 30 GHz signal is realized by using the jump pulse delay sequence to drive the sampler.（4）Based on the designed circuit and other modules in the prototype,the whole system is built and tested,which verifies that the circuit designed in this thesis can trigger the sampler to sample the measured signal.