| Ultrasonic phased array total focusing method is called the"golden algorithm"because of its high accuracy and wide focus range.However,due to the scale of full matrix data required in the imaging process and the complexity of imaging algorithm,the imaging frame rate is low,which limits the application of the TFM in the industrial nondestructive testing field.In order to improve the timing performance of the ultrasonic TFM imaging system under single-layer or two-layer medium,commonly used single-layer TFM imaging schemes are investigated,aiming at the problem that the sound path is difficult to calculate in real-time and the index matrix is too large to be compressed under two-layer medium,a block imaging scheme based on DDR3 hierarchical index storage is proposed.Based on the high parallel capability of FPGA Block RAM and the high data rate of external memory modules,the two-level storage structure splits the synthesis process of the complete TFM image into the time dividsion synthesis of several 128×128 resolution block images.A index update hiding technology is introduced to reduce the time consumption of the sub-image synthesis process.It is deduced that the minimum data rate of the external memory module should be greater than 5GB/s,and the storage capacity should be greater than 512Mb.After layout and routing,signal integrity simulations are performed on single network and bus network.The simulation results of TDR and S parameters show that the hardware design can meet the requirements of DDR controllers and memory modules.The power integrity simulation shows that the DC voltage drop and current density of each power rail meet the requirements,and the upper limit frequency of the PDN impedance of the(1power rail reaches 50MHz under the target impedance of 110mΩ.After sorting out the downloading,storing and synthesizing process of the index matrix,the process is divided into an index cache module,an index update module,and an index storage module.The index cache module and the index update module use asynchronous FIFOs to realize the cross-clock domain data transmission between USB3.0,DDR3 and the system clock.The index storage module controls 32 dual-port RAMs to realize the writing and reading of block index data.Model Sim was used to implement RTL simulation on the above modules,and the functional correctness of each module was verified.Using the PRBS data stream verifies that the DDR3 external memory module can achieve correct and stable data transmission at both 1600MT/s and 800MT/s data rates.The maximum bandwidth of the module can reach 12.8GB/s,and the maximum capacity can be up to 4GB.In inspection test,the API of the three two-layer media TFM images at 256×256,512×512,and1024×1024 resolutions are 6.31,6.29,and 3.58,the frame rates are 31.2fps,7.02fps,and 1.87fps.Compared with the off-line analysis,the API error is within 5%.The results show that the DDR3 external memory module can meet the data rate and storage capacity requirements of index update hiding and the TFM flaw detection system realizes real-time scanning of TFM under single-layer or two-layer medium. |
