| In addition to the pursuit of high computing power,device reliability is also one of the important factors that must be considered in system design for aerospace and airborne devices.Field Programmable Gate Array(FPGA),as a highly integrated semi-custom integrated circuit device,has the characteristics of high parallelism,low power consumption,fast computation speed,and low cost,which can significantly improve the computational capability of starboard and airborne devices.However,the aging problem of on-chip circuits brought about by longtime high temperature and high radiation working environment seriously affects the reliability of the device,and the FPGA aging mitigation problem must be studied in a targeted manner.In this paper,we address these issues by combining the FPGA Dynamic Partial Reconfigurable(DPR)technology with the on-chip stress balancing idea as the guide.The on-chip task scheduling and deployment are optimized to significantly improve the maximum mean time to failure of FPGAs during task execution.The specific work is as follows.(1)A comparative analysis of aging causes that reduce FPGA lifetime is conducted.A heterogeneous reconfigurable structure model and a task scheduling model are established,and a task scheduling strategy based on an improved Genetic Algorithm(GA)is designed with on-chip stress equalization as the optimization target.While reducing the convergence speed of the algorithm,the strategy can keep the mean time to failure(MTTF)in each reconfigurable region of FPGA basically the same when scheduling and executing,and maximize the device lifetime.(2)Based on the above work,to solve the problem of high on-chip resource usage rate during the task execution phase with sufficient resources.The resource usage rate parameter is added in the task scheduling phase,and an optimization algorithm is designed with the constraints of inter-task dependencies and the task deadline,with the common goals of maximizing the system’s mean time to failure and minimizing the resource usage rate.The on-chip resource usage rate is reduced while the device life cycle is guaranteed.The strategy designed in this paper is compared with the stochastic scheduling strategy and the on-chip shortest total task execution time scheduling strategy.The comparison results show that the stress-balancing strategy for heterogeneous systems designed in this paper can extend the system’s mean time to failure by at least 53%.And compared to the homogeneous system’s stress-balancing strategy,there is an improvement of more than 20% in the system’s mean time to failure.When the number of subtasks in the task set is 50 and the total system resources are sufficient,the resource usage rate can be reduced by up to 50 percent while the system’s mean time to failure is basically unchanged.Experiments show that the aging mitigation strategy designed in this paper can significantly improve the mean time to failure of FPGAs,extend their lifetime,and provide a better reliability guarantee for electronic systems containing FPGA devices. |
