| With the development of the information-based electronic era,more and more new mobile electronic products using lithium batteries as energy supply equipment have appeared around us,especially under the call of the national energy-saving and emission reduction policy,as the main force of new mobile electronic products The new energy vehicles of China have sprung up.The rapid rise of new energy vehicles has driven market demand for high-power lithium battery management systems,especially its battery management chips.Coupled with the country’s demand for the localization of chips,it is imminent to be able to develop a high-power battery management chip with independent intellectual property rights.This article is to verify,testability design and physical realization of the digital controller in the battery management chip,and finally reach the tape-out standard.This paper first conducts digital logic verification on the battery management digital controller,and adopts the coverage-driven gray box verification method based on VIP.After simulation model design,verification platform construction,function point extraction,test case design and other steps,it can be used for regression.The automated verification platform for verification and dynamic timing analysis(netlist simulation),according to this verification scheme,greatly reduces the time consumption of battery management digital controller R&D in the verification process.The criterion for the end of the verification work is that the functional coverage and code coverage reach 100%and 96%.This article also uses a full scan design to perform DFT on the battery management digital controller.The introduction of DFT will shorten the test time after the chip leaves the factory,which not only saves test costs but also speeds up the time to market.DFT includes four links:plan determination,DFT module design,scan synthesis,and automatic test vector generation.Finally,the synthesized netlist is formally verified.At the end of this paper,the battery management digital controller is physically implemented.Under the 180nm process,the flattening design process is used for layout design.In the physical realization process,the focus is on the calculation method of the power loop width of the digital circuit of the digital-analog hybrid chip and the clock tree synthesis under the special design requirements of the digital circuit.The final design area of the layout is 690×710μm~2,and the clock frequency is up to 10MHz. |