A Large Current Low Dropout Regulator With High Power Supply Rejection

As the popular of portable electronic devices, power management chips are demanded more and more in quantity as well as quality.Low dropout linear regulator (LDO) is one of the best selling power management chips, due to its precision output voltage, low noise, low power consumption and fully CMOS integrated. The noise of power supply VDD becomes obvious with the development of SOC system, so the power supply rejection (PSR) of LDO is concerned by more and more designers. With the integration of multi-function, a large load current capacity is required. Hence, A CMOS high PSR LDO with a maximum output current of 300 mA is proposed in this paper.A detailed and all-sided PSR theory analysis based on closed-loop LDO is listed, which can help the designer meet the PSR requirement when considering the other performances of LDO.Using small signal model of MOS transistor, Kirchhoff's current/voltage law, and the tool of Mathematica, the PSR with DC gain, poles, and zeros of power stage and six kinds of basic amplifiers in LDO is analyzed theoretically, and proved by the simulation of Cadence Spectre. By tabling the PSR of eight Error Amplifier (EA) composite structures of two stages, the best combination of NMOS differential input amplifier (N-DA)+PMOS input common source amplifier (P-CS) is proposed on account of DC PSR property. The existing architectures of high PSR LDO are classified and analyzed, and one overall design principle is illustrated, that is to obtain a constant gate-source-voltage Vgs of the main power transistor.A LDO based on this principle is designed. It includes the Bandgap part and the LDO_core part. The Bandgap part contains a current bias with high stability, a voltage reference which uses the pre-regulator negative feedback technology to get high PSR performance, and a thermal protection circuit with hysteresis temperature protection. The pass transistor and Error amplifier are the main parts of the LDO_core part. The frequency compensation is also discussed, and one proper scheme is adopted to get the high PSR as well as robust stability. Current limit and short circuit protection circuit are essential in the LDO application and is quantified and designed. The overall system simulation at different process, power supply and temperature is listed and goes with the spec very well. The layout and post simulation are then carried out.A LDO with high PSR and large load current is designed with standard CMOS TSMC 0.18um process. The output voltage range is 1.8 V with a dropout voltage of 170 mV at 300 mA. Post simulation results show that the PSR is 106 dB@ 1k Hz if the output current is 100 mA, and when fully loaded, that is 300 mA, the PSR is 85 dB @ 1 KHz. It is of high performance compared with the other works.