A Two-stage Time Division Multiplexing Analog Front-end For Neural Signal Acquisition

With the development of society and the advancement of medical technology,the requirements for neural signal acquisition and quantification in the field of brain disease diagnosis and neuroscience research are gradually increasing.Each channel of the traditional neural signal acquisition system has a independent set of circuits to realize signal amplification and quantification.Therefore,the circuits between different channels are prone to be different in amplification due to factors such as process mismatch,resulting in offset between channels.In order to reduce the mismatch between multiple neural signal recording channels,and also the power consumption and area of neural signal analog front-end,time division multiplexing technology has become a research hotspot.Detailed discussion of the offsets between AFE channels is performed in this paper.After analyzing the traditional time division multiplexing schemes,a novel four-channel multiplexing scheme is proposed in this paper,which multiplexes the LNA and the VGA among four neural signal channels so that the four-channel neural signal is amplified synchronously,thus effectively improves the channel consistency of the analog front-end and reduces system complexity.Firstly,input cascode and inner common mode feedback loop are adopted to optimize the LNA,thus improves phase margin and achieves a common mode rejection ratio of-135.89d B@50Hz and a power supply rejection ratio of-133.5d B@50Hz,which improves the anti-interference ability of the analog front-end.Secondly,the variable capacitor VGA can provide 5 different gains within a range of0-26d B in order to meet the requirements of neural signal amplification.Finally,a fourth-order gm-C LPF based on the FVFB is designed,which simplifies traditional high order gm-C sturctures.In order to work with the four-channel time division multiplexing structure,the digital DSL used adds register units for each channel,so the four-channel input offset can be eliminated using the same digital DSL.Also,a novel ultra-low-noise current-mode bandgap reference for digital DSL is proposed in this paper.The equivalent integrated output noise in the0.1-100Hz bandwidth is 6.9?Vrms and the bandgap achieves 3.7x offset suppression.The maximum noise introduced by the proposed bandgap reference when applied in the digital DSL is only 3.45?Vrms,which is significantly reduced compared to traditional analog and digital DSL circuits.In addition,this paper proposes an input impedance boost circuit based on DDA buffer,which significantly improves the input impedance.The noise and offset of the DDA buffer are eliminated by embedding the pre-charge buffer in the chopping path.The proposed two-stage time division multiplexing analog front-end is implemented in a SMIC 0.18?m CMOS process with a core circuit area of 1×1.2mm~2,the total chip area is1.4×1.6mm~2.Post-layout simulation shows that the analog front-end proposed realizes amplification of four-channel neural signal synchronously,The gain range of the AFE is34-60d B,the input impedance is 1.6G?and the maximum input offset eliminating range is±300m V.The total equivalent integrated input noise of each channel is 1.66?Vrms within0.1-100Hz bandwidth and the THD of each channel is 0.69%.The analog front-end consumes 30.6?W under 1.2V supply voltage,and each channel consumes 7.65?W.