Designs Of A FFT Accelerator And A Development Board Based On FPGA

Fast Fourier Transform(FFT)plays a crucial role in the field of Digital Signal Processing.With the growing popularity of FFT algorithm,it's required to have diverse algorithms and architectures for FFT implementation in different application areas,such as Radar Signal Processing and Information Communication filed.Besides that,high throughput,high precision,strong real-time and good universality are new directions for the application of FFT.Especially,the flexibility of FFT processor is further proposed by the development of Orthogonal Frequency Division Multiplexing(ODFM).This paper elaborates the design and implementation of a mixed-radix FFT accelerator.Mixed-radix FFT algorithm and single path delay feedback(SDF)pipeline architecture were used to design the accelerator through the comparison and analysis of different algorithms and hardware implementation schemes of FFT.And the proposed mixed-radix algorithm is based primarily on Radix-2/4 algorithms so that the multiplication could decrease and the operating precision could increase.In addition,this paper also improved the SDF architectures which can further optimal design and reduce the complexity of the control program.For the SDF pipeline,it's an effective way to design a strong real-time FFT accelerator with fewer resources.To meet good universality,this accelerator is able to execute FFT of size including 64,128,256 and 1024-points in continuous-flow by re-configuring Mode Register.And some special techniques are adopted to make full advantage of resources,for example,each of the feedback paths can work in both full-depth and half-depth modes.In addition,these techniques also including that twiddle factors stored in a ROM block and addressing counter of ROM can be reused for two kinds of different models,the radix-4 butterfly in the last stage can be configured to a radix-2 butterfly,and both read and write addresses of RAM in reorder module are created by an addressing counter.The proposed accelerator has been implemented on a Xilinx device Virtex-7 XC7VX485T and fully tested by the method of co-simulation using MATLAB and ISim simulation software.According to the measured results,the signal-to-noise ratio(SNR)reach up to 139dB.The synthesis results show that the maximum clock frequency can achieve 287MHz and 1024-point FFT is less than 11us,so the design can meet the requirements of real-time.