| The need for high-speed multifunction protective relays in modern power systems is growing. A relay's fast response and reliable operation to clear faults is essential, especially in the context of smart grids. This research proposes a low-latency hardware digital multifunction protective relay on the Field Programmable Gate Array (FPGA). Taking advantage of inherent hard-wired architecture of the FPGA, the proposed hardware relay design is paralleled and fully pipelined to achieve low latencies in various relay modules which are developed in hardware description language. This low-latency feature allows fast operation and data throughput to reach higher computational efficiency. In addition, the parallelism and the hardwired architecture of the FPGA make the design more reliable in computation than the sequential software-based numeric relay. The case studies demonstrate the effectiveness of the multifunction hardware relay. |
