3D integration with coaxial through silicon vias

3D integration using through-silicon-vias (TSVs) is gaining considerable attention due to its superior packaging efficiency resulting in higher functionality, improved performance and a reduction in power consumption. In order to implement 3D chip designs with TSV technology, robust TSV electrical models are required. Specifically, due to the increase of signal speeds into the gigahertz (GHz) spectrum, a high frequency electrical characterization best describes TSV behavior.;This thesis focuses on coaxial TSV technology due to its superior performance compared to the current existing TSV technology at high frequencies. By confining signal propagation within the coaxial TSV shield, power losses to the silicon substrate are eliminated and unintentional signal coupling is avoided. To the best of our knowledge, coaxial TSV technology has only been characterized using finite element modeling.;The work presented by this thesis focuses on fabricating coaxial TSVs within the confines of standard poly gate CMOS processing. In addition, we perform a high frequency electrical characterization using s-parameters and a thermal stress characterization using micro-Raman Spectroscopy. Furthermore, we investigate applications in SPICE modeling and antenna on chip (AoC) applications utilizing coaxial TSV technology. Our results indicate the coaxial TSV reduces signal attenuation by 35% and time delay by 25% compared to the standard non-shielded TSV technology. Coaxial TSV is consistent with previous TSV results regarding induced silicon stress. Lastly, we propose a 60 GHz antenna design using the coaxial TSV that significantly improves antenna gain compared to previous literature examples.