Compilation techniques for multiprocessors based on DSP microprocessors

This thesis describes a family of practical, suboptimal compilers that produce efficient code for synchronous multiprocessors based on DSP microprocessors. Two separate, but related, compilers are presented. In the first, called the integrated compiler, operation scheduling and code generation tasks are combined in a single entity. In the second, called the divided compiler, operation scheduling and code generation are performed in two separate steps.;A heuristic technique for multiprocessor scheduling under many constraints, called extended list scheduling, is presented with its associated cost function. General characteristics of DSP algorithms from the viewpoint of multiprocessor compilation are discussed and the constraints imposed by real parallel DSP machine architectures are examined for this scheduling approach.;The primary focus of the compilers is the efficient allocation of the resources in the system so as to obtain maximum overall performance. A basic register tracking technique using a modified Least Recently Used (LRU) replacement scheme is developed for allocating pointer registers of DSP chips. Several heuristics are used to maximally utilize the DSP application specific features of DSP chips.;Both compilers can be configured to operate with a wide range of DSP algorithms, multiprocessor architectures, different DSP microprocessors, and a range of other compilation alternatives. A series of experiments were performed with these compilers in order both to compare the architectures of different DSP chips for synchronous multiprocessing applications and also to suggest architectural changes to increase their effectiveness for fine grain, synchronous multiprocessing.