Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts as VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.; A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Four design models currently understood and used in practice by designers have been identified: combinational logic, functional descriptions (involving clocked components such as counters), register transfer (data path) descriptions, and behavioral (instruction set processor) designs. Structured modeling provides recommendations for the use of available VHDL description styles (structural, dataflow and behavioral) so that optimal designs will be synthesized.; A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Graph Compilation parses the VHDL input description into an internal Control/Data Flow Graph representation. The Graph Critic removes inefficiencies introduced by certain language constructs and makes local optimizations in the flow graph structure.; The Design Compilation process involves a collection of algorithms which map the internal representation to a corresponding structural implementation. Portions of the input description may be modeled using different Structured Modeling design models; the Design Compiler will apply the appropriate synthesis algorithm to each section. Behavioral descriptions are processed using algorithms which consider the interrelated effects of storage and function unit allocation on interconnect and total chip area. The VSS system generates a VHDL structural netlist for the data path, and a slate table which captures control information.