A master-slave synchronization method for a SAW-based on-board processing satellite system

Synchronized FDMA inputs from earth terminals to a SAW based on-board, multicarrier, demodulator (MCD) reduces overall satellite system complexity. The synchronization problem of multiple uplink terminals to a geosynchronous (GEO) regenerative satellite processor, with a time-division multiplexed (IDM) downlink, is studied in this thesis. The method considered uses channel probing to provide an uplink propagation delay estimate which can be used by a ground terminal to adjust its transmitter clock phase to ensure synchronization to the satellite clock when the signal is received by the on-board receiver. This method is named transmitter timing recovery and the central concept is to provide global synchronization without the use of a satellite based beacon signal. The method used is based on master-slave synchronization theory, where the satellite is regarded as the master and the terminal as the slave.; Two possible timing offset indicators, the estimated bit error probability and the estimated uplink signal amplitude, which can be used to calculate the timing offset, are identified and examined in the thesis. The estimation methodology follows the maximum likelihood estimation (MLE) principle.; The uplink bit error probability can be estimated to an accuracy of 1/16 th of a symbol interval with probability larger than 0.9 with at least a 4000-symbol long probing sequence for SNR = 4 dB. The uplink signal amplitude is a better indicator in terms of estimation efficiency because in order to get the same estimation probability it requires a 100-symbol probing sequence with operation SNR > 5 dB. The detected uplink signal amplitude is estimated at the output of an on-board MCD. A properly designed probing signal provides a linear relationship of amplitude vs. timing offset on the average. MCD outputs with AWGN at the input are studied in detail. The magnitude distribution follows a Rician pdf. A magnitude estimate is sent to the original terminal in order to have a time-delay estimate that is free of the phase offsets in the MCD.; The performance measures used for the time-delay estimate are (1) the pdf of this estimate, (2) the variance of this estimate, and (3) the number of probing symbols required to get less than 0.5 dB penalty of Eb/N0 in the on-board processor bit error rate due to timing errors with the given timing resolution of T/16. For the worst-case of a one-half symbol time of error, the magnitude estimate algorithm produced satisfactory synchronization 98% of the time. This result is for a 10 dB link Eb/N0 and use of a 4-bit quantizer to transmit the timing error estimate on the downlink TDM channel.; A computer simulation of a complete processing satellite and a communicating terminal shows the interactions between the recovered downlink clock and uplink timing estimate. This simulation includes all aspects of timing recovery, carrier recovery, filtering and data detection in both the terminal and the satellite on-board processor. The delay estimate algorithm is proved workable in this practical system configuration, whereas, in earlier work in this thesis, it could be analysed in restricted situations. The requirement for the downlink to allow the proper operation of the uplink delay estimate is obtained from simulation. The simulated BER results show that with this transmitter timing recovery mechanism used, no significant SNR penalty can be observed with a probing sequence of length 100-symbols.