| Variable-length coding and arithmetic coding, as a consequence of their inherently undelimited codestreams, prove resistant to many known architectural and procedural optimizations. This thesis examines the nature of the contention between coding and operational improvement. Upon establishing a firm understanding of the problem, solutions that address and counteract the illuminated inconsistencies are developed and explored. Optimization is pursued from broad perspectives ranging from system-level process alterations to coder-level designs. For Huffman coding, storage consumption and speed are targeted simultaneously in coder design, permitting no sacrifice in the former. As a separate consideration, encoding design is examined for codes of unrestricted length. Additionally, an existing decoder storage technique of minuscule proportions made more so while the venerable Huffman code generation process is refined with a dual-memory approach. In more general variable-length codings, parallelization is applied for substantial rate enhancement, overcoming what was formerly regarded as an insuperable incompatibility. Parallelization is exploited for the same purpose with arithmetic coding, thereby manipulating to significant advantage an otherwise rigid and complex coding method. The product of this thesis is a selection of novel encoders, decoders, and code generators along with systemic techniques that permit singularly high-rate, compact coding without the common concessions that have crippled earlier attempts documented in the literature. |
