Heterogeneous integration technology for hybrid optoelectronic and electronic device and module fabrication

Various forms of optical computing architectures have promised enhanced processing capabilities well beyond the limits of traditional VLSI technology during the past decade. However, the progress toward realizing this vision has been severely limited by the lack of mature technology to fabricate heterogeneously integrated optoelectronic transceiver arrays (consisting of VLSI electronics with optoelectronic devices) that are necessary to link the functionality of photonic input/output devices with electronic processors. This dissertation describes a research effort that addressed this need by exploring innovative, yet highly manufacturable integration approaches that can be utilized to fabricate hybrid optoelectronic transceivers by integrating thin silicon device layers on bulk electro-optic (e.g. lead lanthanum zirconate titanate-PLZT) and other host substrates.; The two integration techniques developed are: (1){A0}B& P (Bond and Processing) technology involving bonding of bulk-quality thin silicon layer to PLZT followed by low temperature NMOS processing and (2){A0}DDB (Direct-Device Bonding) technology, where circuit layer fabricated in SOI-silicon is thinned and bonded directly to a PLZT substrate. Characteristics of electronic circuits and modulators in integrated Si/PLZT SLMs are measured to be comparable to that of reference devices fabricated in bulk silicon and PLZT substrates. The application of the developed integration technology specifically toward fabricating Si/PLZT spatial light modulator is examined in detail.; The developed device layer grafting technology based on chemo-mechanical lapping and reactive ion etching processes can be applied to assemble miniature "mixed technology" systems consisting of devices fabricated by different manufacturing processes (e.g. CMOS, MEMS, VCSEL and GaAs processes) in a monolithic fashion. The latter half of the thesis details experimental results that demonstrate its applicability toward physically compliant CMOS packaging, 3-D IC stacking, integrated MEMS/CMOS and Si/VCSEL array fabrication.