Genetic algorithm for VLSI physical design

The physical design of VLSI chips is a very complex combinatorial optimization problem. A genetic algorithm approach for solving the VLSI physical design problems is presented here. The algorithm optimizes partitioning, automatic placement & global routing and finally creates input vectors for finding peak power estimation. To show the use of this algorithm, a Graphic User Interface (GUI) is implemented to perform the basic VLSI physical design operations in a user friendly way. Platform used for this application is Borland C++ Builder, version 5.0. Output of this application is kept in text format for future analysis. This thesis report compares the result with existing alternative algorithm to support its validation. The results are found very relevant and it can be concluded that the technique applied is valuable and usable in the proposed domain. Finally various future extensions to the research work as well as to the application are proposed.