Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers | Posted on:2004-11-29 | Degree:M.S | Type:Thesis | University:Rice University | Candidate:Chandrasekhar, Vikram | Full Text:PDF | GTID:2468390011971054 | Subject:Engineering | Abstract/Summary: | | Reduction of the power consumption in portable wireless receivers is an important consideration for next-generation cellular systems specified by standards such as the UMTS, IMT2000.; This thesis explores the design-space for reducing the dynamic power dissipation in a RAKE receiver for the Direct Sequence Code Division Multiple Access (DS-CDMA) downlink. Starting with a reference implementation of the DS-CDMA RAKE receiver, we demonstrate design methodologies for achieving significant power reduction, while high-lighting the corresponding performance trade-offs. At the algorithm level, we investigate the impact of reduced precision and arithmetic complexity on the performance of the DS-CDMA RAKE receiver. We then present architectures for implementing the reference and reduced complexity DS-CDMA RAKE receivers, and analyze these architectures with respect to their dynamic power dissipation. Finally, we analyze clock-gating techniques for reducing the activity rate in both the architectures to achieve further power reduction. | Keywords/Search Tags: | Power, DS-CDMA, Reducing, Receiver | | Related items |
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