Error Control Algorithms and Architectures for Reliable DSP Systems

In the past decades, two major factors have driven the signal and communication system reliability concerns to emerge as new challenges for both researchers and engineers. First, the high-speed low-cost demand translates into high hardware efficiency, which evidently results in less tolerance to any disturbance upon the system that is essentially an error propagator and noise amplifier. In addition, it becomes more challenging for manufacturers to maintain the reliability for very-large-scale integration (VLSI) circuits, and therefore, the design margin will predictably increase. The manufacturing process, circuit operating environment, and the simulation tools can cause circuit glitches and failures that fundamentally degrade system performance. This research will consider reliability issues in signal processing and communication system and will propose various novel algorithms and architectures for coping with these issues. Although general faulttolerant circuit issues have been studied in the past, this thesis is particularly devoted to reliability of the communication system circuit. We investigate the impact of the circuit failures in communication systems. Based on this investigation, new techniques are developed for compensating for the impairment due to these circuit failures. The circuit is viewed as a channel environment while circuit failures are treated as channel noises; in other words, we conceptually erase the boundaries between the circuit and the communication system. Thus, the concepts used in the well-established error correction coding (ECC) theories can be ported into the research of reliable system design. Then, new algorithms and architectures for reliable DSP systems will be proposed from the error control perspective. Three particular communication units will be investigated; they are Viterbi decoders, frequency-selective finite impulse response (FIR) filters, and orthogonal frequency division multiplexing (OFDM) systems.;Novel architectures for Viterbi decoders are proposed for achieving low-latency at minimal complexity cost. It is shown that the proposed three architectures can either reduce complexity by up to 84% or reduce the latency by up to 72.50%.;Novel noise reduction unit (NRU) architectures are proposed for mitigating circuit errors which are deliberately introduced via supply voltage overscaling in order to trade performance for power savings. Compared to conventional designs, the proposed narrow-band architectures can improve the noise reduction performance by 10-22dB while achieving the same or better power savings for narrow-band filters, and broadband architectures can achieve 9-21 dB performance gain while achieving 10.33%-51.74% power savings.;A series of new algorithms and schemes are proposed for detecting and correcting impulse noise in OFDM systems, which cannot be corrected by using any existing error correction coding (ECC) schemes. In a 512-FFT OFDM system at 25dB additive white Gaussian noise (AWGN) signal-to-noise ratio (SNR), simulation results show that the first scheme can effectively correct impulse errors that corrupt up to 9.76% of the received time-domain signal, and the latter scheme is very complexity-efficient though less impulse noise can be eliminated.