Synthesis of synchronous pipelined circuits from high-level modular specifications

Digital circuits have become increasingly more complex at a steadily faster rate over time. As a result, the complexity of the challenge posed to designers to produce efficient, reliable circuits of larger size in less time is growing. This thesis presents a specification language and a synthesis system whose goal is to reduce the amount of time and effort required to design digital circuits and widen the range of people that can build circuits without having to become expert hardware designers.; Our approach relies on novel compiler technology to synthesize highly concurrent, synchronous implementations of circuits, starting from modular, sequential, asynchronous specifications written in our specification language. The modularity and asynchronicity properties of our language make it possible for the designer to think about each module in isolation, which substantially reduces the design time and effort. These properties also enable locality of the specifications, which facilitates developing, debugging, formally verifying and reusing either partial or complete specifications.; Our system is designed with two goals in mind: ease of design and high circuit performance. After experimenting with specifying circuits in our specification language, we can say that developing descriptions using this language approach rather than using Verilog is significantly faster, and the size of the specifications considerably smaller. We have implemented a compiler that takes a description in this specification language and automatically generates a synchronous, concurrent implementation of it in synthesizable Verilog. Rather than having the designer manually coordinate the simultaneous execution of various parts of the circuit, we make it the compiler's job to discover the concurrency in the specifications and expose it in the final implementations. Our algorithms preserve the correctness of the original specifications. After comparing clock cycle and circuit area numbers for our benchmarks with the numbers obtained from equivalent manually-coded Verilog benchmarks, we conclude that our automatically generated circuits provide performance that is virtually identical to the performance of manually written versions. As an important application, we developed an algorithm for efficient, automatic pipelining of unpipelined or insufficiently pipelined circuit descriptions, which implements techniques like stalling and forwarding.