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Implementation of iterative decoding algorithms on digital VLSI platforms

Posted on:2003-09-02Degree:M.EngType:Thesis
University:Carleton University (Canada)Candidate:Zarkeshvari, FarhadFull Text:PDF
GTID:2468390011478717Subject:Engineering
Abstract/Summary:
The complexity-performance trade-off of different iterative algorithms for decoding low-density parity-check (LDPC) codes is investigated and it is shown that min-sum algorithm is a good choice for digital implementation. The effects of clipping and the number of quantization bits on the performance of min-sum algorithm at short and intermediate block lengths are studied. It is shown that min-sum is robust against quantization effects, and in many cases, only four quantization bits suffices to obtain close to unclipped min-sum performance.; We also propose two modifications to min-sum algorithm that improve the performance by a few tenths of a dB with just a small increase in the complexity of decoding. These modifications can close the performance gap between min-sum and sum-product and even outperform the sum-product in some cases. The VLSI implementation of the decoder is investigated, two architectures are discussed, and the main blocks of a parallel decoder are designed.
Keywords/Search Tags:Implementation, Decoding, Algorithm, Performance
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