Process compilation methods for thin film devices

This doctoral thesis presents the development of a systematic method of automatic generation of fabrication processes (or process flows) for thin film devices starting from schematics of the device structures. This new top-down design methodology combines formal mathematical flow construction methods with a set of library-specific available resources to generate flows compatible with a particular laboratory. Because this methodology combines laboratory resource libraries with a logical description of thin film device structure and generates a set of sequential fabrication processing instructions, this procedure is referred to as process compilation, in analogy to the procedure used for compilation of computer programs. Basically, the method developed uses a partially ordered set (poset) representation of the final device structure which describes the order between its various components expressed in the form of a directed graph. Each of these components are essentially fabricated "one at a time" in a sequential fashion. If the directed graph is acyclic, the sequence in which these components are fabricated is determined from the poset linear extensions, and the component sequence is finally expanded into the corresponding process flow. This graph-theoretic process flow construction method is powerful enough to formally prove the existence and multiplicity of flows thus creating a design space {dollar}{lcub}cal D{rcub}{dollar} suitable for optimization. The cardinality {dollar}Vert{lcub}cal D{rcub}Vert{dollar} for a device with N components can be large with a worst case {dollar}Vert{lcub}cal D{rcub}Vertle(N-1){dollar}! yielding in general a combinatorial explosion of solutions. The number of solutions is hence controlled through a-priori estimates of {dollar}Vert{lcub}cal D{rcub}Vert{dollar} and condensation (i.e., reduction) of the device component graph.; The mathematical method has been implemented in a set of algorithms that are parts of the software tool MISTIC (Michigan Synthesis Tools for Integrated Circuits). MISTIC is a planar process compiler that generates process flows for thin film devices from schematics of their structures. The algorithms also include the capability of grading the process flows based on the expected device yield and some empirical factors. The MISTIC software uses a lab-specific database of process recipes and materials to produce process flows for a specific set of laboratory resources and process statistics that help to choose the most suitable process flow in a comparative manner.; Currently the process compiler consists of five modules, viz., the graphical device editor, the database and the database editor, the compiler, and the process viewer constituting a complete design environment. The program has been implemented with approximately 213,800 lines of C code that utilize the X11/Motif library. The compiler in its current version accepts devices with Manhattan-like geometries over a multiplicity of one dimensional slices of the device, hence all calculations are inherently one-dimensional in nature. The compilation procedure has been successfully tested with several conventional integrated circuit devices, e.g., DIODE, CMOS and BICMOS, etc. It has also been successfully applied to Micro-Electro Mechanical System (MEMS) devices such as accelerometer, micro-bridge, micro-motor structures with or without on chip circuits. In each case the compiler has generated a set of process flows which included the established process for that device along with several alternative processes.