| In this thesis, we focus on improving the performance and on reducing the area and the power consumption for hardware implementations of synchronous digital systems.; We address a set of problems in a method based on software pipelining techniques that has been recently proposed to derive synchronous circuits that operate at the maximum throughput. We formulate mathematically those problems and propose methods to solve them. We develop methods to determine schedules for reducing register and phase requirements. Also, we devise methods to simultaneously (1) determine schedules that reduce the required number of registers, and (2) place optimally those registers.; To reduce the power consumption of circuits in CMOS technology, we use multiple supply voltages. Decreasing the supply voltage of a computational element implies decreasing its speed and its power consumption. To satisfy performance requirements, highest supply voltages are used for computational elements on critical paths. The other elements off critical paths can be operated at the lowest possible supply voltages. The problem of minimizing the power consumption using multiple supply voltages is NP-hard in general. We formulate mathematically that problem, and propose two methods to solve it. The first method gives the optimal solution and is based on a branch-and-bound technique. The second one is a heuristic formulated as a linear program.; We also devise an efficient method to speed up algorithms for solving the cost-to-time ratio problem. That problem has many practical applications. Algorithms to solve it have been used to determine the maximum throughput of synchronous circuits.; We implement all the methods we propose here in a tool we coded in C++ and test them on well known benchmarks. |
