Low-power design optimization leveraging multiple threshold and supply voltages

Successful CMOS process scaling has been the key driving force behind the powerful role played by the semiconductor industry in the world today. Scaling has enabled spectacular growth in integration levels and computational abilities of digital integrated circuits. Unfortunately, this scaling is marred by several challenges for the future---reducing power and designing variation tolerant circuits being paramount. This thesis makes contributions to the areas of deterministic and statistical low-power design optimization.; Because of the strong dependence of power on supply voltage, multiple supply design is a very efficient technique to minimize power while maintaining performance. Several issues spanning the design flow hierarchy arise when designing circuits using multiple supply voltages. This thesis presents algorithmic and circuit-level design methods for advancing this idea to realize low-power designs. Topics covered include design of asynchronous level converters, algorithms for supply and threshold voltage assignment including gate sizing, design of robust power delivery systems, design techniques for high-performance dynamic datapath circuits and single supply multiple threshold optimization.; Post-silicon tunable circuit fabrics provide a very effective avenue for combating variations. This thesis presents a new methodology for post-silicon statistical optimization through the use of adaptive body bias. The approach significantly reduces the overheads associated with adaptive body bias while providing tight control over delay and power variation. The work relies on a new statistical optimization framework which emphasizes the use of efficient and established deterministic formulations as tools to guide the statistical optimization. A host of major statistical CAD problems such as gate sizing, threshold voltage assignment, gate-oxide assignment and gate-level channel length biasing are amenable to this methodology.