| Device scaling is directly responsible for Moore's law and has enabled tremendous improvements in MOS (Metal-Oxide-Semiconductor) device performance. As device dimensions shrink, the channel resistance decreases, which in turn allows faster circuit operation. Microprocessor chips operating at 2GHz or higher clock speeds are now available. However, as the intrinsic device continues to improve, parasitic components such as the series resistance in the source/drain region start to limit device performance. Understanding and controlling these parasitic components, through proper design of the device, are therefore essential.; This thesis starts with a general discussion of the issues facing device design in the deep submicron region. After that, the methodology used in this work as well as the important issue of the appropriate metric for comparing device technologies are examined.; Next, the results of a thorough study of the impact of lateral abruptness and gate-extension overlap are presented. The impact of lateral abruptness on series resistance and threshold roll-off is carefully examined. While the conventional wisdom is “the more abrupt the junction, the better the device”, the benefits of lateral abruptness alone on device performance is shown to be less than one would expect from series resistance arguments. At the same time, the gate-extension overlap length is shown to have a significant effect on device performance, suggesting the employment of an additional spacer for tuning the overlap length would be beneficial for device performance.; This thesis concludes by examining the issues of rigorous and accurate calculation of device resistance components; the software developed for processing and analyzing the simulation results for the current study; and grid sensitivity of MOS device simulations. |
