| This thesis investigates the possibilities of realizing superconducting digital circuits using an architecture based on Residue Number System (RNS) arithmetic (as opposed to binary arithmetic), using the superconducting "single flux quantum" (SFQ) as the basic unit of information.;RNS is a complete alternative to the binary logic for digital computations. Binary arithmetic is subject to the well known carry-propagation problem: carry-propagation is necessary for the realization of addition and multiplication operations, and this ultimately limits the performance of binary architectures. RNS arithmetic is intrinsically parallel, modular, fault-tolerant, and most important of all, carry-free. To date, RNS implementation has been attempted, with only limited success, in semiconductor technology. Superconducting SFQ digital technology offers ultra-high speed and almost negligible power dissipation, characteristics not attainable by any semiconductor technology known to date. RNS logic appears to be well-suited for SFQ circuitry, because the modularity in RNS is intrinsically represented by the superconducting hardware. In addition, both SFQ and RNS have high-speed dedicated digital signal processing, rather than general purpose computing, as their primary target applications.;We have developed SFQ circuits using RNS arithmetic and fabricated using niobium Josephson junction technology. A new single module adder, mod5 adder, the main component of a one-decimal digit RNS adder, was designed, laid out and evaluated at low speed with very good operating margins. The mod5 adder combines simple and robust RSFQ elementary cells, both combinational and sequential. The cyclic Josephson shift register is the primary circuit element used to code RNS numbers and perform arithmetic.;A new on-chip high speed test protocol to measure the maximum operating frequency of the mod5 adder was developed. Auxiliary test units for data storage and high-speed clock generation and distribution were designed and experimentally verified. A 10-bit circular shift register used for data encoding was demonstrated to work at high speed with critical margin of +/-6% at 20 GHz. |
