Transistor modeling and low-voltage integrated circuits for radio frequency receivers in CMOS technology

This dissertation explores device modeling and circuit design techniques for the implementation of CMOS radio frequency (RF) receivers.; The resistance of the gate terminal plays an important factor in the frequency response and in the noise behavior of a MOS transistor. Both of these effects are crucial for the design of low noise and high frequency circuits. In this thesis, a small-signal transistor model is developed for high frequency applications such as RF, microwave and optical receivers. The proposed model takes into account the resistance and capacitance of the gate terminal, and their distribution along the width of the transistor. Based on transmission-line analysis of the transistor, expressions for the network parameters as well as the noise behavior are derived in closed form. The modeling equations are of relatively simple form allowing for easy implementation into a circuit and device numerical simulators.; A characterization technique for extracting the effective gate resistance of MOS transistors is also presented. The technique is based on measuring the high frequency network parameters of two transistors with different widths. Based on the proposed procedure, the gate resistance can be uniquely identified from the resistance of the substrate and the nonquasistatic effects. Measurements of n-channel and p-channel transistors with channel lengths of 0.25-mum are used to verify the extraction method. It is shown that the extracted values for the gate resistance of those devices are scalable, bias-independent, and consistent with their physical range.; A comprehensive analysis of the noise behavior of the MOS transistor is also presented. Expressions for the transistor noise parameters (minimum noise figure, noise conductance, optimum source resistance, and optimum source reactance) are derived based on a semiempirical basis. The noise parameters are expressed in practical form which allows for systematic characterization and optimization of the transistor noise behavior.; A circuit topology, named the LC-folded cascode topology, is proposed for implementing low-voltage RF receivers. The proposed topology exploits the complementary transistors (n-channel and p-channel) which are readily available in standard CMOS processes in order to relax the supply voltage requirements of RF circuits. (Abstract shortened by UMI.)...