| With the increasing use of portable devices and the increasing need for security in these devices, side-channel attacks are an increasing threat. Traditional circuit design techniques leave otherwise secure systems vulnerable due to the characteristics of the circuits, rather than weaknesses in the security algorithms themselves. These characteristics, called side-channels, are exploitable because they can be measured and correlated with processed data, potentially giving an attacker insight into the device's secret data. Alternative design techniques such as dual-rail asynchronous designs are capable of minimizing these potential side-channels by decoupling them from the data being processed. However, these techniques are either expensive to implement compared to standard designs or leave exploitable imbalances in the dual-rail implementation itself.;Multi-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD³L). presented in this thesis, offers the security by balancing side-channels both in general and between the dual-rail signals themselves as well as a reduction in circuit overhead comparable to previous design techniques. Results show that the Advanced Encryption Standard cores designed using MTD³L exhibit similar security to previous secure techniques with less design overhead. |
