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Low-power double-sampled delta-sigma modulator for broadband applications

Posted on:2012-08-29Degree:Ph.DType:Thesis
University:Oregon State UniversityCandidate:Shen, WeilunFull Text:PDF
GTID:2458390008993753Subject:Engineering
Abstract/Summary:
High speed and high resolution analog-to-digital converter (ADC) is a key building block for broadband wireless communications, high definition video applications, medical images and so on. By leveraging the down scaling of the latest CMOS technology and the noise shaping properties, delta-sigma (DeltaSigma) ADCs are able to achieve wide-band operation and high accuracy simultaneously. In this thesis, two novel techniques, which can be applied to high performance DeltaSigma ADC design, are proposed. The first one is a modulator architectural innovation that is able to effectively solve the feedback timing constraints in a double-sampled DeltaSigma modulator. The second one is a transistor level improvement to reduce the hardware consumption in a standard Data Weighted Averaging (DWA) realization.;Next, charge-pump (CP) based switched-capacitor (SC) integrator is discussed. A cross-coupling technique is proposed to eliminate parasitic capacitor effect in a CP based SC integrator. Also, design methodologies are introduced to incorporate a modified CP based SC integrator into a low-distortion DeltaSigma modulator. A second-order DeltaSigma modulator was designed and simulated to verify the proposed modulator topology.;Finally, the design of a double-sampled broadband 12-bit DeltaSigma modulator is presented. To achieve very low power consumption, this modulator utilizes the following two key design techniques: (1) Double sampled integrator to increase the effective over-sampling ratio. (2) Capacitor reset technique allows the use of only one feedback DAC at the front end of the modulator to completely eliminate the quantization noise folding back.;A 2+2 cascaded topology with 3-bit internal quantizer is used in this DeltaSigma modulator to adequately suppress the quantization noise while guaranteeing the loop stability. This DeltaSigma modulator was fabricated in a 90 nm digital CMOS process and achieves an SNDR of 70 dB within a 5 MHz signal bandwidth. The modulator occupies a silicon area of 0.5 mm2 and consumes 10 mW with a supply voltage of 1.2 V.
Keywords/Search Tags:Modulator, Broadband, Double-sampled
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