Font Size: a A A

Passive Macromodeling of High-Speed Circuits with Embedded Time-Delays

Posted on:2013-08-11Degree:Ph.DType:Thesis
University:Carleton University (Canada)Candidate:Charest, AndrewFull Text:PDF
GTID:2458390008969259Subject:Engineering
Abstract/Summary:
As designers integrate an ever-increasing diversity of on-board optical components, analog circuits, digital blocks, and Micro-Electro-Mechanical (MEM) devices in each product, ensuring the signal integrity of modern electronic devices has become a challenging task. Coupled with higher operating speeds, sharper excitations, and denser circuit layouts, signal degradation from effects such as reflection, crosstalk, delays, attenuation and Electro-Magnetic Interference (EMI) can no longer be neglected in the modeling and simulation stage of the design cycle. For many components, it is not always possible to find analytical models that accurately capture all of these effects. In such cases, the behavior of these modules is generally characterized by sampled/tabulated data (in the admittance, impedance, scattering, or hybrid domains), obtained either directly from measurements or from a 3D Electro-Magnetic (EM) field solver.;In this thesis, efficient passivity verification and compensation techniques are developed for macromodels based on DRFs obtained from tabulated scattering or admittance parameter data. For passivity verification, the necessary search region is reduced from the entire right-half of the complex plane to a single finite interval along the imaginary axis. For passivity compensation, the residues of the DRFs are iteratively perturbed until the model becomes passive. In addition, an innovative macromodeling technique is presented for tabulated data networks with multiple delays that correspond to periodic reflections. The proposed algorithm is based on a novel DRF formulation that captures multiple delays using only a single delayed rational term. Furthermore, a new passive model-order reduction algorithm is introduced for efficient unified transient analysis of large circuits with embedded delay-based macromodels. The proposed algorithms enable an efficient analysis of long delay interconnects in SPICE-like analog circuit simulators.;Including tabulated data of electrically long networks in SPICE simulators has been a topic of intense research in the past few years. Recently, novel compact macromodeling algorithms for electrically long tabulated data networks were proposed based on approximating the data using Delayed Rational Functions (DRFs). However, DRF-based techniques do not guarantee the passivity of the resulting model, which is necessary for performing stable and accurate transient analysis. In addition, conventional DRF models approximate each delayed response using a separate delayed rational term. For tabulated data networks with multiple delayed responses corresponding to periodic reflections, a large number of delayed rational terms may be needed resulting in a high-order model and slow transient analysis. Also, due to the increasing number and diversity of devices in modern designs, global transient analysis of large systems of delay differential network equations has become a computationally expensive task. Recently, model-order reduction algorithms were introduced for efficient unified simulation of these large time-delay systems. However, these algorithms do not guarantee the passivity of the resulting reduced-order macromodel.
Keywords/Search Tags:Circuits, Model, Tabulated data networks, Passivity, Passive, Delays, Transient analysis, Delayed rational
Related items