| Networks on Chip (NOCs) are increasingly being presented as one of the likely on-chip communication architectures. In this work we present a heterogeneous and hierarchical networking strategy. With a view to extending the NOC design space, we present details about a possible architecture, protocols and physical layer implementation of Token Ring NOCs. Using previously proposed hierarchical global routing schemes, we arrive at a critical network wire length for which NOCs could be most effectively deployed. Adapting an M/G/1 queuing model from off-chip networks, we analyze the likely throughput, latency and efficiency of the proposed communication architecture. Techniques to improve the above metrics are then presented. In particular, the effects of our communication architecture on the expected buffer requirements and the leakage power consumption are highlighted. In conclusion, we discuss the implications for automatic synthesis for networks on chip. |
