| Matrix multiplication is an important arithmetic operation used in several signal and image processing applications. It is a fundamental operation involved in Signal processing techniques such as discrete cosine transforms (DCT), Discrete Fourier transforms (DFT), and Singular values Decomposition (SVD).; Matrix multiplication is a complex problem that involves O (n3) operations on a sequential system and O (n3/p) operations on a parallel system with p processors. Large hardware resources available on FPGAs make it an attractive option for implementing such computationally intensive problems. Current FPGAs contain several multiplexers and fixed-point multipliers that can be used to build floating-point adders and multipliers. The FPGAs also have several configurable logic blocks (CLB's) that can be used to perform calculations concurrently. Thus, algorithms for floating-point matrix multiplication in parallel can be implemented effectively on FPGAs.; This thesis work involves the development of architecture for real-time floating-point matrix multiplication on FPGA. General-purpose, scalable systolic array architecture has been developed. |
