Implementation and evaluation of iterative soft detection/decoding using field programmable gate array

Iterative soft detection/decoding using low-density parity check (LDPC) codes has shown in simulations 3∼5 dB performance gain over uncoded partial response maximum likelihood (PRML) channels at bit error rate (BER) around 10-5. However, for iterative soft detection/decoding to be used in real data storage systems, the implementation of iterative detection/decoding remains a big challenge and the performance of LDPC codes at low BER remains an open question.; To investigate the performance of LDPC codes at low BER, we selected field programmable gate array (FPGA) as simulation platform for high-throughput and reconfigurability. To evaluate different LDPC codes, designing different decoders for different LDPC codes is not practical. Therefore, a generalized LDPC decoder that can be used for a broad class of LDPC codes is developed.; For LDPC code evaluation in an additive white Gaussian noise (AWGN) channel, a high-throughput fully reconfigurable simulator is developed. An AWGN generator on FPGA is developed to speed up the simulation. Using this platform, we investigated the performance of some well-known LDPC codes. BER down to 10-12 of those codes are achieved.; To use LDPC codes in a partial response (PR) channel, a soft output channel detector is required to supply the initial soft information needed by the LDPC decoder. We evaluated the performance as well as complexity of different soft channel detectors and implemented soft output Viterbi algorithm (SOVA) on FPGA.; LDPC codes with iterative soft decoding algorithm have shown extremely good performance, operating near Shannon capacity on AWGN channels. To explore the potential application of LDPC codes with iterative soft decoding in high-density magnetic recording systems, a high-throughput fully reconfigurable FPGA simulator for PR channel with random interleaver and Turbo equalization is developed. Using this simulator, we evaluated some well known LDPC codes and the error floors of those codes are investigated.; Since magnetic recording application requires overall BER of 10 -14 or better, if error floor appears before BER reaches 10 -12, an outer Reed Solomon (RS) code is necessary to deal with the residual errors after the iterative decoder. Knowledge of the BER and the block error rate (BLER) is not sufficient to evaluate the overall performance. We need to know the error statistics of LDPC codes in PR channel. The Turbo product code single parity Check (TPC/SPC) code demonstrates better error statistics compared to LDPC code with column weight of j=3 and larger. We evaluated the error statistics of TPC/SPC code with or without precoders and random interleaver using FPGA.; As a summary, the main objective of this thesis is in developing high throughput FPGA simulator for iterative soft detection/decoding evaluation. Using the high throughput FPGA simulator, we evaluate different LDPC codes at BER down to 10-12. The performance by applying TPC/SPC code before RS code in PR channel is also evaluated.