A High Resolution Time-to-Digital Converter on FPGA for Time-Correlated Single Photon Counting

Time-Correlated Single Photon Counting (TCSPC) can provide not only the time information of a photon, but also the photon density information. Based on the conclusion of usual time interval measuring methods, this thesis presents the scheme of Time-to-Digital Converter (TDC) based on delay line structure, meeting the TCSPC system's requirement for high timing resolution. The TDC design uses Field-Programmable Gate Arrays (FPGA) devices as the platform. The FPGA platform is chosen because the design process of ASIC device not only can be expensive, especially if produced in small quantities, but also the design process is complex due to the long turn-around time and layout phase. This TDC device contains one main coarse counter and two fine counters, which use multiple parallel tapped delay lines to make the find counter more accurate. In this thesis, we use Altera Cyclone III EP3C25 chip to implement the TDC. The simulation of the Verilog code is using ModelSim SE 6.1f; and implement the TDC in Quartus 2 9.0. The histogram of the TCSPC in PC can get from FPGA board; and the communication between the FPGA board and PC by using RS-232. The realized TDC using Verilog, and it was tested by using software simulation and on-board test, and the implemented resulted in TDC system time resolution below 200 ps.