LDPC-OFDM: Channel Estimation and Power considerations

Small cells are low-powered radio access nodes that operate in licensed and unlicensed spectrum that have a range of 10 meters to 200 meters, compared to a mobile macrocell which might have a range of a few kilometres. This dissertation proposes algorithms for the enhancement of small cells installed in high speed rails. The thesis addresses two main points: the link between the small cell and the base station, and the link between the end-users and the small cell. The channel between the small cell and the base station is a fast fading channel due to the mobility of the high speed rail. The first part of the thesis proposes methods to enhance the link between the small cell and the base station using Low-Density Parity-Check codes (LDPC) for fast fading channels. The proposed uses nonuniform reconstruction methods based on the soft output log-likelihood ratio (LLR) provided by the LDPC decoder. The LLRs provide information about the location of the symbols with high probability of being correct. The grid formed under the assumption of a correlated Rayleigh channel affecting the transmitted data is highly nonuniform. Reconstruction of the channel under such assumptions is highly unstable. A signal-to-noise- ratio dependent regularization method is implemented to enhance the performance under imperfect Doppler spread estimation. The second part of the thesis proposes algorithms for the link between the end-user and the small cell. Since power efficiency is a major factor for end-users employing battery powered devices, we propose a Linear Programming (LP) algorithm for signal shaping to minimize the average transmitted power. The other problem the thesis addresses is the minimization of Peak-to-Average Power- Ratio (PAPR) of Orthogonal Frequency Division Multiplexing (OFDM) signals. The PAPR is minimized using a set of phase shifts for the constituting subcarriers of the OFDM signal. The set of phase shifts is determined using a LP approach that minimizes the complexity when the block length is high. A real-time implementation of some of the algorithms is carried out using the TMS320C6713 Texas Instruments board. The results for fixed-point versus floating-point implementation is shown for a different number of precision bits.