A low power parallel processor implementation of a turbo decoder

A novel parallel decoding algorithm for turbo codes is presented, along with its implementation on an embedded Single-Instruction Stream, Multiple-Data Streams (SIMD) processor. The novelty of the parallel algorithm is the simultaneous computation of state metrics and log-likelihood ratios for all trellis stages in the constituent decoder. The results are then interleaved prior to parallel decoding in the subsequent constituent decoder. Implementation of the constituent decoder using the massively parallel SIMD Array Processor of the Atsana Semiconductor J2210 Media Processor achieves speedup factors of 10 or greater for data packet sizes in excess of 512 data symbols when compared to its sequential counterpart as executed by an ARM922T(TM) processor. The bit error rate, performance of the parallel processor turbo decoder implementation lies within 0.1 dB from that of the floating-point reference. The Processors-In-Memory architecture of the SIMD array processor offers a 24% reduction in energy consumption when compared to the low-power ARM922T(TM) core.