| Global positioning systems (GPS) and other emerging global navigation satellite systems (GNSS) are expected to provide accurate location information for various communication and navigation applications. GNSS work well under a wide variety of conditions, but reception is often challenged in narrow urban canyons where tall buildings block the signals, indoors, or in tunnels and underground locations.;Recently, software defined GPS receivers (GPS-SDR) have become popular as they facilitate receiver adaptation to various signal conditions, provide a complete algorithmic control to developers, and reduce development complexity for a broader technology community. The Universal Software Radio Peripheral (USRP) is a popular and affordable RF Front-End used by SDRs (Software Defined Radio) for capturing GPS signals. This and other similar Front-Ends evolve to provide more on-board accelerating capabilities through DSPs and FPGAs for computationally intensive tasks. By delegating demanding tasks, SDRs will be able to process weaker signals and shorten position computation cycles. While increased computational resources provide acceleration opportunities, one should take into account that, for multi-mode GPS-SDR operations, the required resources may vary and be re-configurable, so scalable accelerator solutions will be needed.;This research investigates possible accelerations of early reported FFT-based acquisition algorithm that are most suitable for hardware implementation. Furthermore, this research relies on a parallel, scalable FFT engine implementation presented by the author as part of a requirement for a master's degree in electrical engineering at The University of Texas at San Antonio. The HDL implementation of block accelerator is modeled and synthesized using a modern High Level Synthesis tool, HSL by Xilinx, and verified by using a FPGA Vivado tool. |
