| The front end sample and hold (SH) circuit used in ADCs is a fundamental component that reduce the in dynamic errors, especially with high-frequency input signals.; A "switched capacitors" (SC) circuit topology was used in the realization of the SH circuit, although this technique is not desirable in low-power applications, since the voltage that control the switches is insufficient. In order to avoid associated performance degradation the "bootstrapping" technique was proposed.; Based on the behavioral modeling of each element of the circuit, and by using the Verilog-A language, it was possible to better optimize the circuit with very fast simulations.; Results based on simulations with Cadence using transistors' models of the 0.18mum CMOS technology, and native transistors, gave a 14 bits resolution with a power consumption of 7mW and a bandwidth of 20MHz at a sampling rate of 50MHz.; Based on a layout implementation of the designed circuit, simulations of an extracted model showed a degradation of only 2 bit to end up with a 12 bits resolution, which remains within the limits of the needed operation of the circuit. |
